@hackage clash-vhdl0.7.2
CAES Language for Synchronous Hardware - VHDL backend
Categories
License
BSD-2-Clause
Maintainer
Christiaan Baaij <christiaan.baaij@gmail.com>
Links
Versions
Deprecated
Dependencies (10)
Dependents (2)
@hackage/acme-everything, @hackage/clash-ghc
clash-vhdl
- VHDL backend for the CλaSH compiler
- See the LICENSE file for license and copyright details
CλaSH - A functional hardware description language
CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of CλaSH:
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Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).
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Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
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Higher-order functions, with type inference, result in designs that are fully parametric by default.
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Synchronous sequential circuit design based on streams of values, called
Signal
s, lead to natural descriptions of feedback loops. -
Support for multiple clock domains, with type safe clock domain crossing.
Support
For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum