Where Lions Roam: RISC-V on the VELDT

Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.

This repository contains three parts:

1. The Lion library: a pipelined RISC-V core.
2. lion-formal: formally verify the core using riscv-formal.
3. lion-soc: a System-on-Chip demonstrating usage of the Lion core on the VELDT.

Lion library

Usage:

1. Add lion to build depends section of Cabal file
2. import module in source files import Lion.Core

When connecting the core to memory and peripherals, ensure single cycle latency.

Features

Current Support

Architecture: RV32I (no FENCE, ECALL, EBREAK) -- Default configuration

Future Support

All features will be added in a configurable manner extending the default configuration noted above

• Zicsr, Control and Status Register (CSR) Instructions
• CSR registers
• RV32IM
• Hard IP ALU